As the semiconductor industry continues to improve its process technologies, meeting circuit reliability metrics is becoming increasingly difficult. One circuit reliability metric that has experienced growing concern is that of the Gate Oxide Integrity (GOI).
GOI can be degraded by many factors. Currently, one of the most significant factors in degrading GOI is plasma damage to the gate dielectric. This plasma damage often results from any one of the numerous process steps that presently use plasma. For example, plasma processes can induce damage in the gate dielectrics, resulting in degradation of MOS characteristics due to a buildup of silicon-oxide interface states or oxide traps, or lead to early oxide breakdown. Since the number of process steps using plasma is increasing as the industry attempts to improve its process technologies, the degree to which the industry can control, limit or repair plasma damage, directly correlates to the ability to meet reliability requirements.
Currently there are two major approaches to reducing plasma damage in integrated circuits. The first approach includes eliminating plasma damage at its source by optimizing process and hardware parameters on the plasma tools. Unfortunately, the industry has optimized the process and hardware parameters about as much as it can. The other approach includes mitigating the severity of the plasma damage after it has already occurred by terminating the broken bonds using hydrogen or deuterium gas. Often this damage can likely reappear during the device's operating life, or show up during electrical or thermal stresses, which result in depassivation of the hydrogen. Another approach includes adding additional anneals to the manufacturing process. This approach, however, comes at the cost of additional thermal cycles and increased hydrogen concentration in the chips. Unfortunately, increased hydrogen concentrations have been linked to film delamination problems.
Accordingly, what is needed in the art is an integrated circuit or method of manufacturing an integrated circuit that does not experience the extent of plasma damage experienced in the prior art integrated circuits and methods of manufacture therefor.